According to the present invention there is provided a process for epitaxial deposition of silicon. More particularly, the present invention relates to a high throughput single crystal epitaxial deposition process which achieves increased uniformity, both wafer to wafer and across the wafer surface.
Conventional epitaxial processes are characterized by cycle times on the order of 30-60 minutes. As illustrated by U.S. Pat. No. 3,177,100 entitled "Depositing Epitaxial Layer of Silicon from a vapor mixture of SiH.sub.4 and H.sub.2 " issued to A. Mayer et al, the lengthy cycle time of conventional processes is due, in principal, to the need for protracted cooling prior to removal of the wafer after the deposition reaction. Further delay is occasioned by the consequent requirement of re-heating the susceptor to initiate the subsequent deposition cycle. Repetitive changes in the temperature of the susceptor between each cycle result from the need to cool the susceptor prior to removal from the reaction chamber. It is well known that these temperature changes impart physical stresses which devitrify the crystal lattice in both the susceptor and the substrate. Discontinuities and flaking may also result and further interfere with achieving uniform deposition.
Throughput is, of course, limited by the long cycle times. Because the conventional processes are plagued by low throughput and long cycle times, reactor cleaning is performed only after the deposition runs are complete and the reactor may be taken out of service.
Epitaxial layers on semiconductor wafers have been fabricated by forming a halogen compound of the semiconductor, such as germanium, silicon, or the like, then passing its vapors into a reaction chamber and reducing the halogen with hydrogen. As illustrated in U.S. Pat. No. 3,177,100, conventional processes position the wafer on a susceptor within the reaction vessel; after evacuation, the reaction chamber is purged with hydrogen and the susceptor and wafer are heated to about 1200.degree. C. by rf induction. This temperature is maintained for about fifteen minutes in the flowing hydrogen ambient to clean the wafer surface of any residual oxides. Electrical power to the rf coil is then reduces, thereby reducing the temperature of the wafer and susceptor to within the range of about 1000.degree. C. to 1150.degree. C. Silane, SiH.sub.4, mixed with hydrogen is then introduced into the reaction chamber. Decomposition of silane in accordance with the equation: EQU SiH.sub.4 .fwdarw.Si+2H.sub.2
which deposits an epitaxial layer of silicon on the wafer. The rate of deposition depends, of course, upon the concentration of silane in the reaction vessel and the temperature of the susceptor. Since the deposition rate is temperature dependant, it is important that the wafer be exposed to substantially uniform temperature profile during the deposition run. N or P doping of the silicon may be achieved by incorporating the dopant into the reactant gas flow.
Alternative conventional processes are described E. O. Ernst et al in U.S. Pat. No. 3,424,629 entitled "High Capacity Epitaxial Apparatus and Method" and by V. Y. Doo and E. O. Ernst in "A Survey of Epitaxial Growth Processes and Equipment," SCP and SOLID STATE TECHNOLOGY, October, 1967, pp 31-39. One alternative process utilizes silicon tetrachloride, SiCl.sub.4, as the reactant species in a hydrogen flow. Silicon tetrachloride decomposes according to the following reaction: EQU SiCl.sub.4 +2H.sub.2 .fwdarw.Si+4HCl
which may produce side reaction products depending upon reactant concentration, temperature, pressure and reactor geometry. This process is characterized by virtually identical time, temperature and pressure profiles as the reaction process with silane.
A summary of the deposition run cycle is provided in U.S. Pat. No. 3,424,629 as follows:
(1) Wafers loaded into the reaction chamber; PA1 (2) Argon purge at 10 standard liters/minute (slm) for 9 minutes (min.); PA1 (3) Hydrogen purge at 25 slm for 10 min.; PA1 (4) Rf heating of susceptor to 1200.degree. C.; PA1 (5) Hydrogen etch for 15 min. to remove oxides; PA1 (6) Silicon deposition for 6-14 min., depending upon thickness specification at a deposition rate of 0.8 /min. PA1 (7) Maintain wafer temperature at 1200.degree. C. for 3 min. PA1 (8) Hydrogen purge; PA1 (9) Cool wafers in hydrogen for 10 min.; PA1 (10) Cool wafers in argon unitl wafers reach room temperature for handling; PA1 (11) Remove wafers from reactor.
The total running time for a typical run was seventy-five minutes. Other reactant species, such as SiHCl.sub.3, SiCl.sub.2 or similar halogenated silicon compounds, may be employed.
It will, therefore, be appreciated by those skilled in the art that protracted deposition run cycle times are characteristic of the conventional epitaxial deposition processes. Factors contributing to the long cycle times include the need to cool the wafers to room temperature prior to handling and the corresponding need to re-heat the reaction chamber for a subsequent deposition run.
Thus, it has been found that a new process was required to alleviate these limitations of the conventional processes. According to the present invention, there is provided an epitaxial deposition process characterized by low-level cooling periods which minimize temperature changes between deposition cycles and inter-cycle cleaning so that each new wafer is presented with a substantially equivalent deposition environment. By limiting the need for lengthy cool down, providing for inter-cycle cleaning and modulating gas usage, the process of the present invention achieves higher single crystal epi growth rates that the conventional processes. The single crystal produced thereby is characterized by a more uniform crystal lattice in each wafer and wafer-to-wafer.